Configuration

The main config.json is the primary user interface to the full COmPOSER flow. The example files in EXAMPLES/LNA_1/ and EXAMPLES/PA_1/ are the best reference templates.

Main Keys

Key	Meaning
`datasets`	CSV datasets for inductors, T-lines, capacitors, and CPWDs
`project_name`	Output run directory
`stage_1_config`	Design-specific stage 1 constants
`stage_1_sizer`	Hybrid optimizer entry point, such as `lna_stage_1_sizer.py` or `pa_stage_1_sizer.py`
`stage_1_map_file`	Mapping from hybrid-optimizer output keys back into netlist instance annotations
`design_requirements`	Electrical specs such as frequency, gain, NF, bandwidth, and PA saturation target
`design`	Unsized netlist, sized netlist, and net-weight file paths
`pdk`	Path to `layers.json`
`placement`	Placement constraints and solver controls
`routing`	Router binary and router-constraint JSON
`pdn`	PDN width and gap controls

Design Section

input_unsized_netlist: user-provided starting netlist
input_netlist: sized netlist after hybrid-optimizer mapping
net_weights: RF-critical net weighting JSON

Advice

Use the example configs as templates instead of the root placeholder config
Keep project_name unique when you want to preserve multiple runs
Keep topcell aligned with the top circuit name in the netlist
Replace the mock PDK only if your replacement preserves the layer-file structure the scripts expect

Connected-PDN Configuration

Connected-PDN controls belong in each example's existing config.json. No config_pdn.json is used. Add pdn_routing with router_bin, non-empty vdd_nets and gnd_nets arrays, decap_vdd_net, decap_gnd_net, and decap_count. The selected decap nets must also appear in their corresponding arrays. Legacy scalar vdd_net and gnd_net remain accepted.

Every listed VDD net shares the generated VDD mesh, and every listed GND net shares the generated GND mesh. Multiple ground names must therefore be electrically common; isolated domains need separate meshes. A net cannot appear in both lists. Only power-grid rail targets are expanded across grid layers. Ordinary module pins and non-power nets retain native layer definitions.