What the framework does

Model equations are accepted only after simulator-backed closure.

Input

A SPICE OTA netlist, a topology image, universal HSPICE testbenches, and design targets such as supply voltage, bias current, load capacitance, and design intent.

Core Loop

NEMESIS prompts an LLM to propose symbolic performance equations, compiles them into executable Python, sizes devices through gm/Id data, and validates performance using HSPICE.

Output

A converged scalar OTA model, a vectorized evaluator, sized device parameters, equation history, LLM outputs, and SPICE/model performance reports.

High-level flow

From circuit netlist to verified model

The base driver is llm_aided_modelling.sh. Each block below links to the detailed script operation that implements it.

  1. 1 Create a clean circuit workspace
  2. 2 Simplify the DUT netlist for LLM context
  3. 3 Generate parameter templates
  4. 4 Prepare operating-point extraction
  5. 5 Build gm/Id estimation prompt
  6. 6 Generate target specs with the LLM
  7. 7 Build the initial modeling prompt
  8. 8-16 Iterate model generation, sizing, SPICE, and feedback
  9. 17 Vectorize the converged evaluator

Repository map

Where the framework expects each artifact

llm_aided_modelling.sh
Main orchestration script for one OTA modeling run.
Universal/dut/
Canonical DUT netlists, named by circuit work directory such as 5t_ota.sp.
Universal/otas/
Topology figures and reference netlists used as visual context for the LLM.
Universal/testbenches/
Reusable HSPICE decks for AC, CMRR, ICMR, OCMR, power, PSRR, slew, and operating point extraction.
<WORK_DIR>/
Generated run directory with prompts, LLM outputs, compiled models, sized parameters, and reports.
Specs/
Reference specification JSON files for existing topologies.
docs/
This GitHub Pages website and its self-contained assets.

Detailed workflow

Every operation in llm_aided_modelling.sh

1

Initialize a clean run directory

The script sets WORK_DIR, derives paths for the DUT, netlist, specs, prompts, models, and reports, then removes any existing work directory with the same name. It recreates subdirectories for testbenches, netlist, prompts, llm_outputs, ota_models, ota_model_performance, spice_performance, and specs.

It copies the universal testbenches from Universal/testbenches/ and the selected DUT netlist from Universal/dut/<WORK_DIR>.sp.

2

Generate a simplified netlist for LLM context

generate_netlist_for_llm.py extracts the DUT subcircuit and compacts transistor lines into a cleaner representation. This reduces prompt noise while preserving topology, device names, terminals, model types, and sizing parameters.

3

Create design_params.sp

generate_design_params.py scans the DUT devices and creates a SPICE parameter template containing width and length variables. The default script call sets device length to 180, and later sizing stages update the width values.

4

Generate an operating-point HSPICE deck

generate_op_hspice.py combines the selected DUT and tb_op.sp template into tb_op_temp.sp. The temporary deck is formatted for reliable operating-point table extraction by Python.

5

Build the gm/Id estimator prompt

generate_gmid_estimator_agent_prompt.py prepares an LLM prompt using the simplified netlist plus design context: Vdd, Vss, ibias, channel length, application class, and design intent.

6

Run the LLM to generate specs

call_codex.py sends the gm/Id prompt and topology figure to the selected model. The output is written to <WORK_DIR>/specs/<WORK_DIR>.json and becomes the target file used by the sizer.

7

Generate the first equation-model prompt

generate_stage1_prompt.py creates prompt_stage1.txt from the simplified netlist. This prompt asks the LLM to produce structured performance equations for the selected OTA topology.

8

Generate candidate equations

The LLM consumes the current prompt and circuit figure, then writes llm_output_stageN.json. If this JSON is missing, the same iteration is retried without incrementing the stage counter.

9

Update equation history

extract_equations.py appends the generated equations into equation_history.json. This gives later feedback prompts memory of what has already been attempted.

10

Compile JSON equations into Python

compile_ota_model_script.py converts the structured JSON response into ota_model_stageN.py, an executable scalar evaluator used by the sizing and verification scripts.

11

Run gm/Id LUT-based sizing

design_sizer.py evaluates the compiled model against the generated specs and writes ota_model_estimation_stageN.1.json. With --optimize, it searches for operating points that satisfy gm/Id and saturation constraints.

If the model crashes or fails to size, repair_model.py sends the sizer error log, compiled model, and optional topology image back through the LLM. The repaired JSON is recompiled and retried up to MAX_MODEL_REPAIR_ATTEMPTS.

12

Write sized parameters back to SPICE

update_design_params.py maps the gm/Id sizing result into design_params_updated.sp. This file drives the HSPICE testbenches with model-derived widths and lengths.

13

Run HSPICE characterization

perform_hspice_simulations.py runs the universal test plan with the selected DUT, updated parameters, DUT wrapper, and local run directory. It produces a JSON report and appends sweep data to design_sweep_log.csv.

14

Extract transistor operating points

extract_op.py parses run_op.lis into op_results.json. These simulator operating-point values are then supplied to the model evaluator for a more direct comparison against SPICE.

15

Re-run sizing in verification mode

design_sizer.py --verify --opjson evaluates the same compiled model using extracted HSPICE operating-point data. The result is written as ota_model_estimation_stageN.2.json. If verification output is missing, the iteration is discarded and regenerated.

16

Analyze mismatch and create the next prompt

feedback_manager.py compares HSPICE performance with equation-model performance using a default 15.0 percent threshold. If all equations are accurate, convergence is declared. Otherwise the script writes prompt_stageN+1.txt with targeted feedback and continues.

17

Generate a vectorized final evaluator

After convergence, vectorization_agent.py converts the scalar evaluator into ota_model_stageN_vectorized.py. The vectorized script is intended for faster batched evaluation once the equation set has already passed SPICE closure.

Universal verification

Reusable circuits and testbenches

The Universal/ directory makes the flow portable across OTA topologies by separating DUT netlists, topology figures, and simulation templates.

Interface adapter

dut_wrapper.sp exposes a common DUT_UNIVERSAL interface: vp vn vout vdd vss ibias vb2. DUT_HAS_VB2 selects whether the underlying DUT consumes the extra bias pin.

Characterization decks

The current test plan covers input common-mode range, output common-mode range, AC gain/UGF/phase margin, operating point, power, CMRR, PSRR+, PSRR-, and slew rate.

Run isolation

Each run copies templates into <WORK_DIR>/testbenches before editing generated parameters, keeping the universal source templates reusable.

Adapting NEMESIS

How to modify the flow for another circuit

  1. Add the DUT netlist. Place the SPICE netlist at Universal/dut/<new_work_dir>.sp. The main subcircuit should be named DUT, or pass/update the subcircuit extraction behavior in generate_netlist_for_llm.py.
  2. Add a topology figure. Put a matching image at Universal/otas/<new_work_dir>.png. The LLM uses this as visual topology context during spec estimation, model generation, and repair.
  3. Normalize the pin interface. Use the universal OTA pin order vp vn vout vdd vss ibias, or vp vn vout vdd vss ibias vb2 when the design needs the second bias. Set DUT_HAS_VB2 and VB2_DC in the copied testbenches or parameter templates when needed.
  4. Edit script configuration. In llm_aided_modelling.sh, update WORK_DIR, PARENT_DUT_FILE, NETLIST_FILE, SPEC_FILE_TEST, FIGURE_FILE, MAX_ITER, model settings, and design-context arguments such as Vdd, ibias, L, application, and design-intent.
  5. Check the testbenches. Verify supply names, bias direction, load capacitance, common-mode levels, sweep ranges, and measurement names in Universal/testbenches/. Add or modify templates if the new circuit needs metrics beyond the OTA test plan.
  6. Run, inspect, and iterate. Execute the driver, then inspect generated prompts, llm_outputs, model performance JSON, SPICE reports, and repair logs. Persistent mismatch usually indicates missing topology context, incorrect pin mapping, incomplete measurement extraction, or specs that are not feasible for the selected topology.

Using the repository

Basic run sequence

python3 -m venv llm_venv
source llm_venv/bin/activate
pip install -r requirements.txt

# Configure API credentials required by call_codex.py.
# Make sure HSPICE is available on PATH.

bash llm_aided_modelling.sh

The driver currently deletes and recreates WORK_DIR at the start of a run. Preserve any useful generated artifacts before reusing the same work-directory name.

About us

NEMESIS connects LLM-derived analog equations with simulator-grounded verification.

NEMESIS was developed at the University of Minnesota as a research framework for operational transconductance amplifier design automation. It focuses on making compact performance models useful in practice by repeatedly checking and repairing equations against HSPICE results.

What the paper introduces

The paper presents NEMESIS, short for NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring. Given an OTA netlist and schematic, the framework identifies circuit primitives, derives performance equations, and improves those equations through a SPICE-based repair loop.

Why it matters

OTA sizing often alternates between quick hand equations and slower transistor-level simulation. NEMESIS keeps the speed of analytical models while anchoring them to simulator data, making the generated equations more reliable across biasing ranges.

Reported results

In a commercial 65 nm PDK, the paper reports results on five OTA topologies, with SPICE-verified equations achieving less than 7% average relative error and roughly 4622x faster post-convergence evaluation than full SPICE evaluation.

Paper citation

Cite NEMESIS

Subhadip Ghosh, Ramesh Harjani, and Sachin S. Sapatnekar, "NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring," arXiv:2607.05657, 2026.

@misc{ghosh2026nemesis,
  title={NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring},
  author={Ghosh, Subhadip and Harjani, Ramesh and Sapatnekar, Sachin S.},
  year={2026},
  eprint={2607.05657},
  archivePrefix={arXiv},
  primaryClass={cs.AR},
  doi={10.48550/arXiv.2607.05657}
}

Contact

For more information

For questions about NEMESIS, implementation details, or research collaboration, contact Subhadip Ghosh.

Subhadip Ghosh

Department of Electrical and Computer Engineering, University of Minnesota

ghosh211@umn.edu